In one aspect, the present invention relates to magnetron-enhanced plasma-assisted chemical vapor deposition (CVD) reactors and associated methods for performing high rate deposition of dielectric, semiconductor and conductor films. In addition, the technique can be used for low temperature nitridation and oxidation. In still other aspects, the invention relates to apparatus and methods for performing in-situ multiple integrated circuit processing steps, and to deposition techniques for implementing conformal coatings and planarization.
The early gas chemistry deposition techniques which were applied to semiconductor integrated circuit fabrication used thermally-activated chemistry to deposit from a gas onto a heated substrate. Such chemical vapor deposition (CVD) of a solid onto a surface involves a heterogeneous surface reaction of gaseous species that adsorb onto the surface. The rate of film growth and the film quality depend on the surface temperature and on the gaseous species available.
More recently, plasma-enhanced low temperature deposition (and etching) techniques have been developed for depositing diverse materials, including metals such as aluminum and tungsten, dielectric films such as silicon nitride and silicon dioxide, and semiconductor films such as silicon.
The plasma used in the plasma-assisted CVD processes is a low pressure reactant gas discharge which is developed in an RF field. The plasma is, by definition, an electrically neutral ionized gas in which there are equal number densities of electrons and ions. At the relatively low pressures used in plasma-assisted CVD, the discharge is in the "glow" region and the electron energies can be quite high relative to heavy particle energies. The very high electron temperatures increase the density of disassociated species within the plasma which are available for deposition on nearby surfaces (such as substrates). The enhanced supply of reactive free radicals makes possible the deposition of dense, good quality films at lower temperatures and at faster deposition rates (300-400 Angstroms per minute) than are possible using purely thermally-activated processes (100-200 Angstroms per minute). However, the deposition rates available using plasma-enhanced processes are still relatively low. In addition, there are other difficulties associated with chemical vapor deposition and plasma-enhanced CVD processes. These difficulties are discussed below. Using plasma-assisted chemical vapor deposition, silicon nitride is formed from silane, nitrogen and ammonia reactants as follows: EQU SiH.sub.4 +NH.sub.3 +N.sub.2 .fwdarw.Si.sub.x N.sub.y H.sub.z ( 1)
Undesirably, the concentration of hydrogen in the deposited silicon nitride can be as high as 25-35 atom percent. The presence of hydrogen in structures formed relatively early in the IC fabrication process and the hydrogen diffusion which results during subsequent high temperature fabrication steps can cause non-uniform electrical characteristics. In particular, as the layer thicknesses and spacings are decreased to provide increasingly dense integrated circuit structures, hot carrier injection problems associated with hydrogen make such high hydrogen content unacceptable. Even for final passivation films, the presence of hydrogen can create problems.
The trend toward ever greater device densities and smaller minimum feature sizes and smaller separations in VLSI integrated circuits imposes increasingly stringent requirements on the basic IC fabrication steps of masking, film formation (by deposition or growth), doping and etching. For example, it becomes increasingly difficult to form conformal coatings on stepped surface topography or to achieve planarization of interlevel dielectric layers, even when using plasma-enhanced CVD films. FIG. 1 represents a typical cross-section of an IC step topography in which a first film such as a conductor layer 11 has been formed over the existing stepped topography of a partially completed integrated circuit (not shown) and is undergoing the deposition of an interlayer dielectric layer 12 such as silicon dioxide. This is done preparatory to the formation of a second level conductor layer (not shown). Typically, where the mean free path of the depositing active species is long compared to the step dimensions, (and where there is no rapid surface migration) the deposition rates at the bottom 13, sides 14 and top 15 of the step topography are proportional to the associated arrival angles. Since the bottom surface arrival angle is a function of the depth and width of the trench, the thickness of the deposited layer at the bottom 13 of the trench tends to be less than that at the sides 14 which, in turn, is less than the thickness at the top 15.
Increasing the pressure used in the deposition process would increase the collision rate of the active species and decrease the mean free path. This would increase the effective size of the arrival angles and increase the deposition rate at the side walls 14 and bottom 13 of the trench. However, and referring to FIG. 2A, this would also increase the arrival angle and associated deposition rate at the step corners 16. For steps separated by a wide trench, the resulting inwardly-sloped film configuration and the associated cusps 17 provide a less than ideal coverage. Nonetheless, the film topography can be made planar (to facilitate formation of the subsequent second level conductor layer) by the use of conventional planarization techniques. In contrast, and referring to FIG. 2B, where the steps are separated by a narrow trench, for example in dense 256 kilobit VLSI structures, the increased deposition rate at the corners 16 encloses a void 18. The void is exposed by a subsequent planarization procedure and allows the second level conductor to penetrate and run along the void and short the conductors and devices along the void.
Thus, the current state-of-the-art of the plasma-assisted CVD technique can be summarized as follows. Plasma-assisted CVD reactors provide maximum deposition rates of approximately 300-400 Angstroms. However, problems exist in meeting the needs of future plasma deposition technology, for example in eliminating or decreasing high hydrogen impurity levels in plasma CVD nitride films and in the difficulty in achieving conformal step coverage and effective planarization in the topography of small-dimension VLSI devices.
The requirements for any successful future plasma deposition technology are several. The capability for forming low hydrogen silicon nitride and the requirements of topography in terms of step coverage and planarization have been mentioned. In addition, the capability for forming interlevel plasma oxide films as well as low hydrogen-content oxynitride films is desirable. Oxynitride films have different dielectric properties from oxides and nitrides and are being implemented as gate dielectrics in both volatile and nonvolatile IC technologies. Furthermore, it is desirable to have the capability to form interconnects and metalization of materials such as silicides, aluminum and refractory metals. Increasingly, and in particular as multi-level mask conductor and dielectric structures are implemented, it is desirable to have an in-situ process which is capable of performing a multiplicity of steps without removing the wafer from the chamber by simply changing the reactant gas chemistry and operation conditions. This latter statement is demonstrated by two examples.
Consider first the use of silicon nitride as a passivation layer. As mentioned, low-hydrogen content nitride is desirable to eliminate hot carrier problems, but low-hydrogen nitride films can be highly stressed. One approach which permits the use of low-hydrogen nitride passivation layers is to first deposit phosphosilicate glass (PSG) to alleviate the stress, then deposit the low-hydrogen content nitride. Obviously, throughput would be increased and the defect density would be decreased if the two deposition steps could be performed in the same reactor.
A second example involves the use of aluminum. Sputter-deposited aluminum is the favorite metal for interconnects despite the several problems associated with its use. For example, pure aluminum undergoes electromigration which causes cracks, voids, etc. Aluminum also forms hillocks or columns which can punch through insulating layers. It is possible to dope aluminum with copper to decrease electromigration, but copper itself is very hard to etch. A better solution is to form a multi-layer structure of aluminum/tungsten/aluminum. Again, throughput would be increased by using chemical vapor deposition to deposit the three layers in the same reactor. Perhaps more important than all is that CVD aluminum will have much better step-coverage than sputter-deposited aluminum films.
Furthermore, in implementing the dense, complex, process-sensitive present and future integrated circuits structures, it is and will be desirable to have a plasma deposition technology which is adaptable to automatic cassette-to-cassette wafer handling, both for off-loading wafers from the cassette into the processing chamber and returning the wafers to the cassette after processing.
Finally, throughput and particulate control will be helped by the use of load lock mechanisms. Load lock mechanisms not only decrease pumping and processing time, but also decrease exposure of the very susceptible VLSI structures to contaminants.